Recent advances in digital hardware and digital processing techniques have provided electrical designers powerful tools for creating a multitude of electronics applications. Many functions which have traditionally been implemented exclusively in the analog domain are now being realized via discrete, digital architectures. In many cases, a digital processing element can process a digital representation of a continuous, analog waveform with more accuracy and with less added noise than by a corresponding analog processor. However, even though digital processing is superior to analog processing in many aspects, there are still many situations in which an analog representation of a discrete digital element or series of elements is either necessary or desired. For example, a particular system may require a final output in the form of a physical, quantifiable, analog parameter such as voltage, current, resistance, light, sound, etc., even though an intermediate signal processing stage employs an efficient and accurate digital signal processor. In such cases, a digital to analog converter (hereinafter referred to as DAC) receives a digital data element from the intermediate signal processor and produces the physical parameter as a function of the digital data element. Often, the digital signal processor is implemented in software or firmware which is executed by a microprocessor or microcontroller, and a voltage level is the desired output.
Many forms of DACs exist in the prior art. Commercially available DAC integrated circuits exist which utilize various techniques to receive a digital data element and produce a corresponding voltage. However, such DAC integrated circuits can be expensive relative to the overall cost of the product into which the integrated circuit will be designed. A type of DAC especially applicable to a microprocessor based digital signal processor is the pulse width modulation (PWM) DAC. A PWM/DAC, illustrated in block diagram form in FIG. 1, includes a pulse generating unit 2, a low-pass filter element 4 and a sample-and-hold element 6. In general, the pulse generating element 2 receives a digital data element which represents a value corresponding to a unique voltage level. The pulse generating element 2 produces a periodic waveform having a duty cycle proportional to the value of the digital data element. For an N-bit digital data element which defines 2.sup.N discrete states, the pulse generating element 2 produces a periodic waveform having 2.sup.N equal length time slots. Each time slot is either completely filled by a pulse or completely void of a pulse, and the number of time slots containing pulses corresponds to the value of the digital data element. The filter element 4 receives the periodic waveform and provides a voltage, proportional to number of pulses per period of the periodic waveform produced by the pulse generating element 2, to the sample-and-hold element 6. The sample-and-hold element 6 samples the output of the filter element 4 and produces a voltage corresponding to the value of the digital data element. The PWMIDAC is especially suited to a microprocessor based digital signal processor because the pulse generating element can often be implemented by the microprocessor itself. Thus, the added cost in hardware is due only the filter element 4 and the sample-and-hold element 6, which may be significantly less than a DAC integrated circuit.
The lowest duty cycle condition of the PWM/DAC occurs when the value of the digital data element is such that zero time slots per period contain a pulse. The lowest non-zero duty cycle condition of the PWM/DAC occurs when the value of the digital data element is such that one and only one time slot per period contains a pulse. The filter element 4 must receive several cycles (e.g., 10 cycles) of such a low duty cycle waveform in order to produce a steady state output. Since the output of the sample-and-hold element 6 will not settle at a constant value until the filter element 4 produces a steady state output, a PWM/DAC in this example has associated with it an inherent time delay, or conversion delay, of approximately (10)(2.sup.N)(T.sub.TS), where T.sub.TS is the time duration of one time slot. As an example, for a 13 bit digital data element with) T.sub.TS =1 .mu.S, the inherent time delay is on the order of 82 mS. An 82 mS DAC conversion time is unacceptable for many common applications.
There is a need for a for a relatively low cost DAC with conversion times significantly less than those exhibited by prior art PWM/DACs; thus it is an object of the present invention to provide a DAC with a production cost significantly less than commercially available DAC integrated circuits.
A further object is to provide a DAC with a conversion time significantly less than prior art PWM DACs.
Other objects of the present invention will in part be evident and will in part appear hereinafter. The invention accordingly comprises the process involving the several steps and the relation and order of one or more of such steps with respect to the others and the apparatus possessing the construction, combination of elements, and arrangement of parts exemplified in the following detailed disclosure, and the scope of the application of which will be indicated in the claims.